Pursuing higher performance and density of FPGA devices by migrating to a smaller-geometry silicon process presents challenges with power consumption issues. The power consumption of a device based on the 90nm process rises considerably along with the increase in performance and density. To obtain the desired performance and density without the power consumption penalty requires an improvement to the logic structure in the FPGAs.

Research conducted by E. Ahmed and J. Rose concluded that FPGA logic fabric with wider look-up tables (LUTs) provides better performance, while FPGA logic fabric with narrower LUTs is more cost effective. Other researchers reached similar conclusions.