Strategies for ASIC Board-Level Validation
With the advent of multi-million gate System-On-a-Chip (SOC) ASIC devices, the validation effort required has become a significant challenge, and can amount to more person-months of effort than the development of the devices themselves.
This paper describes strategies for ASIC board-level validation. It presents the advantages of undertaking an open systems approach to the development of validation strategies, and highlights the opportunities that exist to maximize circuit and embedded software reuse from the validation effort for eventual deployment in the ASIC device end-user context.
A number of validation board architectures are presented, along with a discussion of how these architectures can be extended into a validation system to facilitate chipset testing.
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