Trends in IC design are driving the need for more advanced analysis, which in turn, is driving the need for more accurate device-level data. With gate counts increasing, clock speeds accelerating, geometries shrinking, metal layers increasing, and design cycle times getting shorter and shorter, designers need more than a traditional extracted SPICE netlist or timing file for analysis. Given that more than 80% of designs are failing first silicon, today’s analog/mixed signal system-on-chip (AMS SoC) designs require a comprehensive approach to parasitic extraction that satisfies the needs for accuracy, performance and detailed analysis. Without an accurate, high-performance extraction tool, there is a strong probability of non-functional design.

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