Progressing integration and system-on-chip approaches increase the complexity of advanced designs. Data preparation, mask and wafer manufacturing have to cope with these designs while achieving high throughput and tight specifications. One of the biggest variables in a production mask processing flow is the actual design being produced. Layout variability can invalidate process settings by introducing conditions outside of the range the process is calibrated for. Characterization of how parameters such as density distributions, CD distributions, minimum, and maximum CD impact yield will no doubt remain proprietary. However, the ability to characterize a layout by these geometric parameters as well as lithographic parameters is a common need. Gathering this knowledge prior to the processing can contribute significantly to the efficiency of applying process recipes once the correlation has been made. The capabilities of a statistical layout analysis are demonstrated and practical applications in mask data preparation and manufacturing are discussed.

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