Traditionally, simulation-based dynamic verification techniques—such as directed tests, constrained-random simulation, and hardware acceleration—have been the work horses of functional verification. As modern day SoC designs become more integrated, the only way to advance significantly beyond dynamic verification is to increase the adoption of static verification. This paper will summarize a variety of static verification techniques, including RTL lint, static RTL checks (which include low power structure verification and clock domain crossing verification), sequential formal checks, application-specific formal solutions and assertion-based formal property verification.
Note: By clicking on the above link, this paper will be emailed to your EE Times log-in address by Mentor Graphics.