Predicting the performance of a design before it is implemented is a challenge faced by every design engineer. IC designers have myriads of tools and models at their disposal to simulate their designs even before fabrication. However, when considering the full system design, there are very few components for which accurate models exist. This means that a full system-level verification has to be done manually by the designer via budgeting, spot checks, modeling, visual inspection and modifications based on previous experience. Unfortunately, this leaves a potential for errors and bugs in the design. In some cases, several board revisions are required to achieve the intended functionality and performance.