Specifying DDR and High Speed Timing Requirements Using PCB Constraints
The traditional method used by semiconductor silicon manufacturers for specifying high speed timing requirements is tedious data sheet parameters and simulation models. The system designer uses this information for the devices in the system to evaluate if the hardware meets timing specifications and thus can be expected to operate reliably. Ultimately, the real question the hardware designer wants answered is “How do I hook it up?”. The approach presented here is different: the processor/controller manufacturer solves the system timing problem once, and than a guaranteed solution is communicated to the ultimate system designer via industry-standard PCB routing rules. Critical to the success of this approach is a naturally constrained system solution set and industry
standard components. This approach is particularly well suited to embedded JEDEC DDR and DDR2 memory interfaces.
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