As cycle times in high-performance digital systems shrink faster than simple process improvement allows, sequencing overhead consumes an increasing fraction of the clock period. Domino circuits are particularly popular in high-speed systems, but suffer from three sources of overhead: clock skew, latch delay, and imbalanced logic. This overhead can exceed 25 percent of the cycle time in aggressive systems. This paper describes the principles of skew-tolerant domino circuits that use overlapping clocks and eliminate latches to hide the overhead.