Simultaneous Multi-Scenario Timing Optimization for Today's Complex, High-Performance Digital IC Designs
When designers work on timing closure, they want the timing analysis that is driving the optimization to exactly match the timing analysis they will use to sign-off the design. Furthermore, when working on timing closure, designers want the timing and optimization
engines to be able to comprehend—and work with—all of the possible scenarios simultaneously,
and to automatically adjust the design to meet all of its timing specifications.
Unfortunately, existing computing engines and algorithms have proved themselves inadequate for
the task. This paper first introduces the concepts of corners and modes that result in the different scenarios for which the design has to be verified. The paper next considers the problems associated with the various conventional techniques that have been employed in an attempt to solve the multi-scenario timing optimization problem. Finally, the paper introduces a new approach that can perform true concurrent multi-scenario timing optimization without requiring any changes to existing design tools and flows.
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