If you’ve ever used an FPGA in an asynchronous system with multiple clocks, or in one that uses a clock with a frequency or phase that differs from the one your FPGA uses, your design can encounter metastability problems. Unfortunately, if your design falls into one of these system scenarios, there’s no way to completely eliminate metastability, but there are several methods you can employ to reduce the likelihood your system will encounter it. Let’s take a closer look at what causes metastability and then examine some methods we can employ to attack it.