Simplifying FPGA Pin Assignment Closure
Closing on a pin assignment that will meet requirements from both the PCB and FPGA environments is becoming more challenging. On one side of the interface, ever-increasing FPGA performance, density, and I/O count are placing tighter board constraints on the layout of the signal to and from the FPGA. On the other side, timing, congestion, and signal integrity of ever-faster signals on the PCB are placing constraints on FPGA pin assignment.
The latest EDA survey conducted by EE Times tends to reflect this challenge. Two-thirds of respondents said that their latest design uses two or more programmable devices. They also selected “getting the FPGA to work on the PCB” as the second most challenging part of FPGA design projects.
Until recently, very few tools or processes existed to assist with FPGA pin assignments, but this is changing. In this article, I’ll look at the causes of pin assignment changes in today’s design environments, describe the implications of such changes, and review the different tools available to simplify and automate FPGA pin assignment closure.
Please disable any pop-up blockers for proper viewing of this Whitepaper.