Silicon Design Chain Cooperation Enables Nanometer Chip Design
Shrinking process technology nodes, increasing chip complexity, more complicated design verification tasks, and shorter times-to-market have multiplied the difficulty of designing systems-on-a-chip (SoCs). It’s not enough to design a chip that meets specifications—that chip must also make a successful transition to a manufacturing environment. To meet this objective, an EDA tool vendor and a silicon foundry—Cadence Design Systems and TSMC—have combined their technologies and expertise to ease the complexities of SoC design, offering specific process-related design enhancements for improved manufacturability.
Recognizing the problems with silicon design methodology over the past several years, EDA vendors and foundries have introduced products and services directly aimed at simplifying both front-end and back-end chip design. However, these efforts were often divided because of the process that separates the end of design from the beginning of chip manufacturing—silicon processing. For nanometer designs at 130 nm and below, TSMC has developed Design Reference Flow 4.0, which concentrates on back-end (post-synthesis) design and incorporates Cadence design technologies and several design techniques to increase the probability of first-time silicon success.
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