Sign-off Power Optimization for ASIC Designs
This article describes the PowerMAX-PR sign-off power optimizer, and how it is used on a design project. The first two sections below define the sign-off power optimization problem, and describe some existing approaches to solving it. This is followed by a description of PowerMAX-PR’s capabilities and the algorithms it uses. PowerMAX-PR was applied to two blocks from an enterprise networking chip designed by Solarflare Communications, and thus one section is devoted to explaining how this was done, and the results that were achieved. The final section of the paper draws conclusions on the effectiveness of sign-off power recovery, and its value in an ASIC design flow.
Please disable any pop-up blockers for proper viewing of this Whitepaper.