Unlike traditional design rule checks (DRCs), which have a clear pass or fail definition, yield issues, such as density and antenna checks, are dependent on a number of variables, resulting in a yes, no or maybe paradigm. These issues, which have a major impact on total chip yield, have typically been identified as design constraints and embedded in DRC rule files. But there is little in the way of information on how a change in layout relates to overall improvement in yield. With advanced processes of 130nm and smaller, designs that are verified DRC clean can still result in poorly yielding or even non-functioning silicon. For this reason, a new method of communication is needed between designer and manufacturer for determining yield issues. Rather than being provided information on a simple pass/fail basis, designers need immediate access from the manufacturer to how various layout characteristics impact chip yield. This new communication loop is the first and necessary step in adopting and implementing a design for manufacture (DFM) flow. Such an approach identifies trouble spots and provides the important data that allows the designer to determine a cost/yield analysis. Designers will be deciding on and implementing a “fix or fab” methodology, resulting in greater yield and control.

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