Selecting an I/O Architecture for Your FPGA Design
In the not-too-distant past, designers used FPGAs primarily as prototyping vehicles. However, during the last decade FPGA data rates have increased dramatically, and they now rival those of CMOS ASICs. The surge in system performance convinced designers to take advantage of the flexibility inherent in FPGAs to create easy-to-upgrade products for a wide variety of markets, including communications, consumer, industrial, military and automotive applications.
The fast data rates of modern FPGAs allow designers the flexibility to create their own application-specific buses. However, these designers must immediately deal with the challenges of running I/O at high speeds. Factors such as channel-to-channel skew, jitter, and aperture window size limit the theoretical data rates of the FPGA’s specifications. To address these issues, FPGA system designers are following the lead of their ASIC-focused predecessors and adopting I/O architectures that inherently reduce the effect of these factors.
This application note describes today’s most popular I/O architectures and explores the factors that degrade the I/O performance of each architecture. Finally, we offer some pointers for selecting an appropriate I/O architecture for your application.
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