This document focuses on physical layer testing of the transmitter (TX) and receiver (RX) ports of PCI Express (PCIe) devices. BER testing not only checks the device or chipset function, with the proper setup, it can also test transmitter and receiver parametric capabilities. This provides important information for the
chipset designer.

This document highlights how to implement a total BER test solution with the Agilent J-BERT N4903A High-Performance Serial BERT. It provides details on how to
set the equipment up, for example, for pattern editing,
and explains the capabilities for functional and parametric test including jitter injection for jitter tolerance tests.