Seamless CVE from Mentor Graphics Speeds Verification for Xilinx Virtex-4 and Virtex-II Pro FPGAs with Embedded IBM PowerPC Processors
Embedded processor-based Platform FPGAs have placed new demands on tool providers. With hardware and software flows converging on the same device, users are looking to retain their productivity through simplified, intuitive and interoperable tool environments. The current generation of Xilinx Platform FPGAs with powerful RISC processors and multimillion-gate capacities requires powerful and matching co-verification methodologies. With the availability of Mentor Graphics Seamless CVE, you now have access to an ASIC-strength, best-in-class debug solution. This article introduces the concept of co-verification, and describes its role, relevance, and realizable benefits in the context of programmable systems. The paper also explains the development work done in cooperation with Mentor Graphics to extend existing IBM PPC405 HW/SW co-verification solutions to more effectively target Xilinx devices.
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