Scalable Verification: A Comprehensive Flexible Methodology for Complex Multimillion Gate Designs
Functional verification is a major challenge for electronic designers today. Total system complexity is growing as more functionality is integrated to differentiate products, including analog/mixed-signal content, embedded processors, and their respective software. With this increased integration, design size grows, verification complexity skyrockets, and the number and length of tests increases. When things go wrong, it’s more difficult to find out why, and the cost of late changes or even respins is prohibitive. To meet these challenges and reap the rewards of system-on-chip design, engineering teams need a scalable verification solution that addresses all aspects of the design cycle and reduces the verification gap. This paper examines why and how the Mentor Graphics Scalable Verification solution addresses the fundamental challenges facing design teams in order to improve design productivity, design quality, time-to-market, and return on investment.
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