System complexity continues to grow exponentially. This results in more buses with more high-speed signals, which translates into more chances of signal integrity problems. Complex protocols, varying data payloads, and multiple operating modes create more opportunities for signal integrity to be affected by pattern-dependent jitter and delay, and for simultaneous switching noise to eat up time and voltage margins. This application note is intended for Digital designers in research and development who design complex, high-speed digital circuits (such as printed circuit boards and integrated circuits) for the computer and communications industries.