As the IC industry accelerates towards the adoption of 32nm and 28nm process nodes, designers face significant new challenges with digital routing. These challenges to sub-nanometer routing—including complex DRC/DFM rules, increasing rule count, very large (1B transistor) designs, and multiple optimization objectives—are stressing the ability of the digital routing engines to meet timing, manufacturability and yield targets. This paper describes the 28 nm routing challenges and presents solutions available from the electronic design automation (EDA) perspective.