Robust SEU Mitigation With Stratix III FPGAs
The benefits of FPGAs over ASICs become ever more compelling as rapid-process technology scaling and innovation provide ever-greater speed, density, and power improvements. However, along with technology scaling come other effects that could previously be ignored. One of these effects is increased susceptibility to soft errors caused by single event upsets (SEUs). With careful IC design, the soft error rate per bit decreases at 65 nm; however, each process technology generation offers twice the logic density, doubling the number of configuration RAM (CRAM) bits.
A secondary effect of FPGAs becoming denser and more capable is that they now tend to sit at the heart of the system, often in the data path. This offers the designer integration of a system into a programmable chip. With this change, FPGAs are now a primary silicon choice for many systems. These systems demand high reliability, and thus modern, high-end FPGAs – such as Altera’s 65-nm-based Stratix III – must offer robust SEU mitigation.
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