Requirements for a True Mixed-Level TLM-RTL Design Environment
Today’s incredibly large and complex digital ICs (ASICs, ASSPs, and SoCs) can easily contain tens of millions of logic gates. The only realistic way to create and verify designs of this size and complexity is to use a mixture of pre-defined intellectual property (IP) blocks and application-specific logic.
In this case, the pre-defined IP blocks – which may be internally developed, but which are often acquired from third-party vendors – are used to implement well-known functions such as general-purpose microprocessor cores, special-purpose digital signal processor cores, peripheral functions, memory interfaces, and high-speed data interfaces. This leaves the designers free to focus their time and resources on the application-specific (“secret sauce”) logic that will differentiate this product from any competitor offerings.
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