The Xilinx Implementation Tools offer designers a degree of flexibility and control over their design that enables quick time-to-market and increased clock speed. One feature of the software is Relationally Placed Macros (RPMs). RPMs provide order and structure to related design elements without requiring you to specify their absolute placement location on the field programmable gate array (FPGA) die. This gives the implementation tools more flexibility to meet timing requirements, whereas floorplanning requires absolute placement of the logic. Without reserving an entire area of the FPGA die, RLOC constraints allow you to increase speed and use die resources efficiently by placing logic blocks relative to each other. The implementation tools can also optimize and merge other logic within the RPM.

This paper describes the Relationally Placed Macros (RPMs) feature of the Xilinx Implementation Tools, and presents a VHDL test case.