The Spartan-II family, combined with a vast soft IP portfolio, is the first programmable logic solution to effectively penetrate the ASSP marketplace. Xilinx recently announced the availability of LogiCORE Reed-Solomon products. These cores are proven and optimized in their FPGA implementation. Smart-IP Technology is used, taking advantage of the relational placement constraint capabilities of Xilinx development software tools to leverage the distributed memory and segmented routing of the FPGAs. As a result, the user can easily customize the Reed-Solomon core and always achieve a predictable, highly-optimized implementation with the highest possible performance, which is unaffected by device size and surrounding user logic.

Xilinx also provides Reed-Solomon IP through AllianceCORE partners Memec Design Services (MDS) and ISS. The Reed-Solomon solutions from Xilinx on a Spartan-II device are good examples highlighting the concept of a programmable ASSP. Both MDS and ISS are members of the Xilinx AllianceCORE program and have a wealth of other IP cores that cater to a variety of applications.

This paper explains the theory behind Reed-Solomon error correction, and discusses how a variety of practical Reed-Solomon encoding/decoding solutions can be implemented using Xilinx Spartan-II family FPGAs.