Reducing Physical Verification Cycle Time
The size and complexity of nanometer integrated circuit (IC) design and the volume of geometric content for related layouts have skyrocketed, and extensive changes have occurred in the processing requirements for nanometer design processes. Physical impacts that could once be ignored now have measurable electrical effects. As a result, ensuring that the original design intent is maintained is increasingly difficult. New verification strategies are clearly needed.
This paper discusses Calibre, which provides the most comprehensive and forward-looking functionality for performing DRC, LVS and DFM simulations. Through hyperscaling technology and the ability to utilize specialized cell processor architecture, Calibre ensures the fastest possible runtimes. With incremental verification and debug, Calibre lets engineers validate the impacts of design modifications without waiting for DRC runs to complete. These capabilities offer the ability to dramatically reduce the total physical verification cycle time.
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