For a robust OPC solution, it is important to isolate and characterize the detractors from high quality printability. Failure in correctly rendering the design intent in silicon can have multiple causes. Model inability in predicting lithographic and process implications is one of them. Process model accuracy is highly dependant on the quality of data used in the calibration phase of the model. Structures encountered during the OPC simulation that have not been included in the calibration patterns, or even structures somewhat similar to those used in calibration, are some times incorrectly predicted.


In this paper, a new method for studying VT5 model coverage during OPC simulations is investigated. Employing the method described can help in avoiding catastrophic misses in the correction phase and allows for a robust approach to MBOPC.

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