The flexibility offered by field-programmable gate arrays (FPGAs) has made design iterations an integral part of the design process. Traditionally, engineers quickly wrote hardware description language (HDL) for their design, ran synthesis and place-and-route, programmed the FPGA, and verified the design functionality directly in hardware. If a performance issue or a functional bug was discovered, appropriate modifications were made to the HDL, followed by a time-consuming resynthesis and re-place-and-route to obtain a new FPGA bitstream and re-testing in hardware. The resulting long runtimes make this traditional approach impractical. This article will explore an incremental design approach that provides run-time savings and preserves quality-of-results.

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