AISP’s based on processors plus embedded FPGAs allow designers to achieve maximum performance by instantiating hard-wired computing elements, such as the requisite number of multipliers, and application specific I/O in an easily customizable part. Leveraging this capability, designers can architect SoC devices with the optimum tradeoff between performance, area and costs for implementing the desired target application. Using this design approach, memory bandwidth is flexible and bus allocation is again under user control for optimal results. Embedded FPGAs offer new choices to designers as compared to conventional approaches used today.