This paper describes RapidIO, a high performance, low pin count, packet switched system level interconnect architecture. The interconnect architecture is an open standard which addresses the needs of a wide variety of embedded infrastructure applications. Applications include interconnecting microprocessors, memory, and memory mapped I/O devices in networking equipment, storage subsystems, and general purpose computing platforms. This interconnect is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications with performance levels ranging from 1 gigabit per second to 60 gigabits per second. Two families of RapidIO interconnects are defined: A parallel interface for high performance microprocessor and system connectivity and a serial interface for serial backplane, DSP, and associated serial control plane applications. The serial and parallel forms of RapidIO share the same programming models, transactions, and addressing mechanisms. Supported programming models include basic memory mapped I/O transactions, port-based message passing, and globally shared distributed memory with hardware-based coherency. RapidIO also offers a very high degree of error management and provides a well-defined architecture for recovering from and reporting transmission errors. The RapidIO interconnect is defined as a layered architecture which allows scalability and future enhancements while maintaining backward compatibility.

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