The RapidIO interconnect design accommodates the next-generation performance and transport requirements for chip-to-chip and board-to-board communications within embedded computer systems. Targeted for an initial bandwidth of between 1 and 12 Gbytes/sec per device pair, RapidIO technology is particularly well suited to applications that must meet stringent latency constraints and exceed the performance capabilities of a single processor.

RapidIO offers tremendous potential for increasing the bandwidth and, hence, overall performance of computing systems using multiple processors. This article will examine tests on a multi-computer system to exploit the potential of RapidIO. The test data validates the performance claims made by the RapidIO community and demonstrates the architecture’s maturity for use in real-world applications.

Reprinted with permission from Embedded Computing Design/Winter 2003. Article © OpenSystems Publishing.