Deep-submicron (DSM) processes have made it impossible to sign off a gate-level netlist with full confidence that the final physical implementation will meet all design requirements. Since interconnect has a significant impact on timing closure, and signal integrity issues cannot be handled without layout specific information, design signoff can no longer be accomplished solely by logic synthesis. Because of this, two new concepts have arisen: physical synthesis, and physical prototyping. Physical synthesis is logic optimization together with place-and-route. We define physical prototype as a circuit description with enough physical information to deliver a design signoff.

For more information on physical synthesis and physical prototyping, visit Monterey Design Systems’ Web site.