Today’s SoCs demand increasing performance with high energy efficiency, but yet require flexibility to address late specification changes, post-silicon modifications and product derivatives. ASIPs close the gap between highly optimized fixed-hardware data path implementations and standard processor IP, and efficient architectural exploration is at the heart of any ASIP design process. Designers need to rapidly explore the impact of different architectural choices on power consumption and performance, ideally using real-world application C-code as part of the design flow. This white paper explains the architectural tradeoffs available to an ASIP designer, how to trade off performance vs. area, and why an ASIP design can still maintain full C-programmability while being optimized for a certain application domain.