Raising the RTL Abstraction Level and Design Conciseness with SystemVerilog
With the advent of advanced HDLs that provide new and powerful language constructs, such as SystemVerilog, hardware modeling styles can now be enhanced both in terms of abstraction levels and overall efficiency. Developing concise, accurate designs entails learning how SystemVerilog features can be effectively used to design efficient and synthesizable models for both ASICs and FPGAs. This paper will focus on the impact of new extensions and constructs in SystemVerilog on hardware designs and describe the usefulness and compatibility of these constructs vis-à-vis pure Verilog constructs.
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