Preventing Structural Faults in Design: Clock and Resets
Metastability problems commonly occur when a signal is transferred between circuitry in unrelated or asynchronous clock domains. The designer cannot guarantee the setup and hold requirements in this case, because the signal can arrive at any time relative to the destination clock. This paper will discuss structural faults in asynchronous clock and reset designs that may cause metastability issues or glitches and the way structural verification methodology should be improved to detect those issues early in design cycle. This paper will also present some design techniques to avoid such faults.
Read Part 2: Preventing Structural Faults in Design: Data Path
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