Today’s field-programmable gate arrays (FPGAs) have progressed far beyond just gates and I/O. The new generation of devices not only contain millions of gates, but have become application-specific integrated circuits (ASICs) and systems-on-a-chip (SoCs). As these architectures increase in capacity, functionality and performance, FPGA developers are not only faced with design challenges related to achieving timing closure, but they must also find ways to reduce the overall design cycle time. They must find efficient synthesis and simulation methods, as well as techniques and methodologies to reduce place-and-route runtimes.


This paper provides guidance for choosing the right FPGA design tools and methodologies for a productive design flow while preserving FPGA freedom of choice.

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