As more dedicated functional blocks are embedded into FPGAs architecture, the challenge to a synthesis tool to accurately handle the functionality and timing across these blocks increases. This paper highlights Precision RTL’s capability to be able to propagate clock values across a FPGA’s PLL (Phase Locked Loop) block. As opposed to the traditional approach of treating a PLL block as a black-box, Precision RTL can extract the primary input clock and also calculate the values of the output clocks of the PLL. This enhanced capability translates to lesser dependency on user intervention (to setup clocks) and to a better timing estimation by the synthesis tool.

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