In a practical system, one is limited to a finite number of bits in the words used for the filter input, coefficients and filter output. Most current digital signal processors provide arithmetic logic units and memory architectures to support 16 bit, 24 bit, or 32 bit wordlengths, however, one may implement arbitrarily long lengths by customizing the multiplications and additions in software and utilizing more processor cycles and memory. Similar choices can be made in digital hardware implementations. The final choices are
governed by many aspects of the design, such as required speed, power consumption, SNR, cost, and so on.

This paper discusses practical considerations in Fixed Point FIR Filter implementations. It discusses scaling FIR coefficients, choosing the FIR filter output word, and quantization noise in FIR filters.