Power-Saving Clock-Gating Technique is an Inseparable Part of SoC Design
Toshiba Pointer and Pitfall design insights are written to help designers cope with evolving system-on-a-chip (SoC) design issues and to support product-planning decisions. This design insight takes a closer look at today’s higher performing SoCs, where clock gating is increasingly becoming an inseparable part of the SoC design technique due to strict chip power requirements. In theory, clock-gated designs can achieve both lower power consumption and improved timing performance compared to similar non-clock-gated designs. This paper provides a quick analysis of clock-gating techniques and “dos” and “don’ts” for your next design.
Please disable any pop-up blockers for proper viewing of this Whitepaper.