Very high-performance multi-core DSPs are increasingly used in telecommunications access, edge and infrastructure equipment to process voice, video and radio signals. Flexible, adaptable and field programmable DSPs typically consume more power and area than their less nimble counterparts. If we can design a high-performance DSP that is sufficiently power-efficient, we will have the ideal solution for these target applications. A better understanding of power dissipation is required. What is alarming is the power crisis that arises in CMOS technology in 90nm and below. This paper discusses various design techniques that can be used to alleviate and circumvent that power crisis.