As chips become more highly integrated and faster, designers face more challenging problems in managing power consumption. To create products that will be competitive in the marketplace, designers must stay ahead of the curve with regard to techniques for reducing power consumption. New techniques are emerging which offer major advances in improving the power efficiency of silicon and all of these techniques will be needed simply to stay even with the battery life expectations of customers. When selecting silicon, designers should look for the hardware support these techniques require, such as multiple low-power modes for implementing sophisticated power-management strategies, and support for voltage and frequency scaling. System architecture should provide for aggressive power management and energy conservation with considerations at all levels including HW power partitioning, provisions for partitioned.