The rise in System on Chip (SoC) size and speed, as well as the increase in leakage current in Very Deep Sub Micron (VDSM) process technologies, have led to power consumption challenges across a broad range of designs that have not been viewed as supply limited or “low power” designs. Power issues may limit functionality or performance and significantly affect manufacturability and yield. Design techniques aimed at improving performance may therefore fall short if power is not considered. Fortunately, techniques such as multi-voltage islands and dynamic scaling of both clock frequency and threshold voltage can conserve power while delivering high performance.

Developed by Synopsys Professional Services, this white paper describes proven techniques in SoC power management and discusses power optimization and analysis methodologies that enable predictable power closure.