Power Considerations in 90 nm FPGA Designs
Managing your system power within budget is essential to maintain reliability in your system. Failure to do so may cause components to break down and reduce reliability.
The semiconductor industry’s rapid move toward 90 nm silicon processes benefits the performance and cost aspects, but places enormous pressure on power budgets. As transistor sizes decrease, leakage current (and hence static power) increases exponentially. Dynamic power also increases, with increasing system speed and larger design density, but in a more linear fashion.
Today, many designs have 50/50 static and dynamic power dissipation. According to International Technology Roadmap for Semiconductors (ITRS) projections, static power is increasing exponentially at every process node; thus, innovative process technologies are imperative.
With the adoption of FPGAs in more markets and systems every year, driven by increasing performance/density and decreasing price, FPGA power consumption within the entire system is becoming critical. Leading FPGA vendors are already adopting new techniques to mitigate static and dynamic power consumption.
Please disable any pop-up blockers for proper viewing of this Whitepaper.