Planning SystemVerilog Adoption
Design demands have grown exponentially over time as fabrication capabilities and geometry sizes have improved drastically. The verification methodologies have not kept up and not changed a whole lot over at least four decades. Different attempts have been made at advancements but the solutions were proprietary or left to user’s imagination, at best. SystemVerilog amalgamates these previously attempted, disjoint technologies by extending a well known design language—Verilog. However, adopting new verification methods often seems unmanageable. This paper provides a new way for digital design and verification groups to easily adopt SystemVerilog. The paper opens with a historical review of how transaction-level modeling (TLM) has been used for design, followed by an explanation of how SystemVerilog can be useful for taking verification to the transaction level. We will look at how the Open Verification Methodology (OVM) addresses the vastness of the SystemVerilog language. The paper will finally propose a “next-generation” approach to design and verification management using SystemVerilog to improve verification methodologies by a couple of decades.
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