The Precision Physical Synthesis product offers a suite of tools that allows users to create optimum FPGA designs. The PreciseView tool helps you to manually modify the layout to achieve timing closure. It ensures that edits produce legal results and provides immediate timing feedback. Even so, a great deal of effort may be required in high-end designs. What happens if a small change (more common in larger, complex designs) is required? Starting over is simply not acceptable. This paper describes a placement reuse design flow to address those inevitable last-minute engineering change orders (ECOs) with minimal disruption to your product schedules. The combination of advanced deterministic naming algorithms with smart placement overlay commands provides a comprehensive placement reuse flow to manage ECOs. This flow is vital to creating a practical and predictable design environment, and should be well understood by the end user.

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