Power, performance, and area (PPA) is a phrase the IC design community commonly uses when describing the three key areas to focus on in optimizing an IC design. Performance has traditionally been the primary focus, but as designs have moved to smaller, more advanced process nodes, and as switching activity has become a dominant component in power consumption, power is growing in importance.

How can strict power specs be achieved without sacrificing performance during the implementation phase of the IC  design process? Many of the challenges of achieving low-power during place-and-route (P&R) relate to how well the P&R software handles multiple power domains and the kind of optimizations the software performs throughout the flow to achieve low power goals.

This paper examines how the Siemens Aprisa P&R tool addresses these power challenges in two main ways:

  • Through PowerFirst implementation technology that reduces total power consumption
  • Through multi-power domain methodology support