Most hardware designers who are qualifying field programmable gate array (FPGA) performance normally run “bake-off”-style software benchmark comparisons of FPGAs from different vendors to determine which vendor provides the largest margin for their timing requirements. Unfortunately, out-of-the-box design compilations do not produce equivalent or fair performance comparisons because different software tools have different default timing analysis and optimization behaviors.

Altera’s Classic Timing Analyzer, in general, calculates all possible register-to-register and complex clock structures using the worst possible assumptions. Xilinx’s Trace timing analyzer does not analyze many of these complex structures, and comparing the software tools on this basis unfairly penalizes Quartus II performance. The Classic Timing Analyzer makes the most stringent assumptions, allowing users to see possible problems by default. This can cause users comparing the two tools to perceive, initially, that Quartus II performance is inferior, which is not the case in actual practice. This paper addresses the differences in timing analysis between Altera’s Classic Timing Analyzer and Xilinx’s Trace, and explains how to configure the tools to provide equivalent performance comparison.