As data rates exceed 6 Gigabits per second (Gbps), the size of many physical structures within backplane interconnects become significant. For example, the electrical length of a typical backplane connector produces standing wave resonances between 2 GHz and 3 GHz. This can result in dramatic changes in crosstalk, mode conversion, and insertion loss deviation at fundamental frequencies of interest.

Such passive interconnect issues can be further compounded by the common mode issues and other challenges silicon vendors and chip designers must confront. This paper focuses on the major performance limitations seen across numerous backplane designs and proposes methods to improve the overall performance of such systems.