PCI Express (PCIe) 3.0, and soon 4.0, introduce new test challenges for next generation designs. At 8 GT/s bit rate, the interconnect performance bandwidth of PCIe 3.0 is double that of PCIe 2.0, and will double again to 16 GT/s with the introduction of PCIe 4.0. As of PCIe 3.0, receiver testing became mandatory and for the first time the reference point for receiver specifications was moved inside the chip. This application note discusses how Agilent’s high-performance J-BERT M8020A enables PCIe receiver testing.