PCI Express 4.0 Controller Design and Integration Challenges
Designs that will include PCI Express 4.0 functionality must keep all of the updates to the specification in mind, from the data rate increase, to the use of re-drivers and retimers, updated link equalization, effective communication through the PIPE interface, and handling the increasing numbers of packets per clock cycle. Design decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper will describe the market adoption and expected use of PCIe 4.0, what is new in the specification, and the top three challenges the new specification brings to controller designers.
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