Generating test patterns with sufficient parameter space coverage has always been one of the critical steps towards building good OPC models. The advancement in technology node requires continues updates to OPC modeling test patterns. The traditional approach relies heavily on experiences gathered from older technology nodes. It often requires rounds of costly test tape out. Here we propose an automated flow for test pattern generation utilizing a fast full chip pattern matching algorithm. We describe the implementation of the flow. We also present experimental results and discuss the benefit and challenges of the proposed flow.

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